M I C H A E L   F.   K L E I N  PHD

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VLSI Design & Consulting









Today's VLSI challenges are unfamiliar territory for many designers. What may have been traditional ASIC or COT designs a few years ago are now commonly having timing closure, signal integrity, power distribution, and physical design capacity problems, to name just a few. What were subtle or insignificant physical issues a few years ago are now common causes of multi-month schedule slips, low yield, and field failures. Off-the-shelf ASIC tools and design flows are insufficient to solve these issues for complex 0.18 micron and below designs. Most designers are untrained and inexperienced in these issues as well.

Physical design expertise is needed today more than ever before. Physical design starts at architectural definition to help establish realistic project goals, estimate project costs and resource requirements, assess implementation risks, and identify required skills and tools. Throughout implementation, physical design works with logic, test, manufacturing, and other disciplines on chip implementation and integration to ensure "no surprises" late in the project.

With electrical engineering degrees from Caltech and the UC Berkeley and over 15 years of technical and managerial high-performance VLSI experience in both large and small Silicon Valley chip companies, Dr. Klein's background is uniquely suited to deliver high-value physical design and consulting services for ASIC and COT VLSI projects.

For more details, please see Dr. Klein's background page.

For more information, please contact Dr. Klein directly.